The present invention relates generally to static random-access memories of the type including a plurality of insulated-gate field-effect transistors (IGFETs) fabricated on a monolithic semiconductor chip and, more particularly, to a five-transistor static memory cell which can be fabricated employing complementary metal-oxide-semiconductor transistor technology on bulk single-crystal semiconductor substrates, referred to hereinafter as "CMOS/bulk".
As is well known, a digital random-access memory comprises a multiplicity of individual storage cells configured into a large array on an integrated circuit chip and suitably addressed, for example, by word and data bit lines. Each individual cell is capable, during a writing operation, of being set by an external signal into either of one of two distinct states. So long as power supply voltage continues, the cell remains in the set state indefinitely, or until it is changed to the other state by a subsequent writing operation. The state of the cell can be sensed during a reading operation to retrieve stored data, preferably in a non-destructive manner, i.e., which does not change the state of the memory cell.
In the design of large memory arrays, a critical design consideration is the number of memory cells that can be put on a chip, i.e., the packing density. To achieve a high packing density, the number of devices per memory cell must be small. Thus, in this respect, a five-transistor cell is preferable to a six-transistor cell. Indeed, reducing the per-cell transistor count by only one is significant. Other design considerations are minimizing power dissipation and ease of implementation. With respect to the design consideration of minimizing power dissipation, the type of latch circuit selected is important. For example, a known latch circuit having inherently low static power dissipation comprises a pair of cross-coupled inverters, with each inverter including a complementary pair of IGFETs, i.e., one N-channel IGFET and one P-channel IGFET. With respect to the design consideration of ease of implementation, it is preferable to design memory cells which can be implemented on bulk single-crystal substrates, in contrast to devices implemented employing silicon-on-insulator (SOI) technology, such as silicon-on-sapphire (SOS) technology. More generally, it is desirable to employ memory cells which can readily be fabricated employing conventional CMOS/bulk technology.
One general type of prior art static memory cell particularly pertinent in the context of the present invention includes a latch circuit of the type referred to above. Specifically, this type of memory cell comprises a pair of CMOS transistor inverters cross-coupled in a bistable latch or flip-flop configuration, with the output of each inverter connected to the input of the other inverter. Two complementary data nodes are thus defined. Each inverter includes one P-channel IGFET and one N-channel IGFET, with the IGFET gate terminals tied together and serving as the inverter input, and the IGFET drain terminals tied together and serving as the inverter output.
While such a memory cell comprising two cross-coupled CMOS inverters requires four transistors just to implement the latching function, it has the advantage of extremely low static power dissipation.
For writing data into and reading data from such memory cells, two general circuit techniques are known, as well as a number of variations.
In the first general circuit technique, a pair of input/output gating transistors operating in push-pull are employed. Thus, the complete cell requires six transistors, four in the latch and two in the gating circuitry. The gating transistors are respectively connected between the two data nodes and two external lines, DATA and DATA, for both writing data into and reading data from the cell. The gating transistors are enabled at the same time for either a reading or a writing operation. For a reading operation, the DATA and DATA lines are coupled through the gating transistors to the two data nodes to assume the respective complementary logic states on the two data nodes. The condition of the DATA and DATA lines is then sensed by suitable sense circuitry, remote from the memory cell, but on the same semiconductor chip. For a writing operation, the DATA and DATA lines are driven by an external driver circuit to the proper logic states and, when the gating transistors are enabled, force the data nodes through a push-pull action to the desired logic state. By way of example, such a memory cell is disclosed in Ando U.S. Pat. No. 4,150,441.
Such a six-transistor memory cell, while quite suitable in operation, has the disadvantage that six transistors are required in its implementation.
The second general prior art circuit technique is to employ four transistors in the latch or flip-flop, but only a single gating transistor connected to just one of the data nodes. Thus, a five-transistor cell results. The single gating transistor is connected to a single input/output point of the memory cell, and is used to either sense the state of the cell for reading, or to write information into the cell for writing.
While the single gating transistor has the advantage of reducing transistor count, it has a disadvantage of making the writing operation more difficult to achieve in a reliable manner because the more forceful push-pull action available with two gating transistors is not available. In general, to write into the five-transistor cell, the impedance of the single gating transistor must be as low as possible to enable the cell to change state to accept new information. However, when reading the information contained in the cell, it is necessary that the gating transistor have a relatively high impedance in order to prevent residual voltages on the DATA line from overriding and altering the contents of the memory cell.
Several approaches have been employed for minimizing this problem. One general approach is to fabricate the gating transistor with an impedance sufficiently high that the cell can be read out non-destructively. When it is desired to write information into the cell, the control gate of the gating transistor is overdriven by employing a voltage higher than the normal supply voltage to the memory cell. The higher voltage is generated by an on-chip voltage multiplying circuit. This technique is described, for example, in Dingwall U.S. Pat. No. 4,189,782, and in the literature reference A. G. F. Dingwall and R. G. Stewart, "16K CMOS/SOS Asynchronous Static RAM", IEEE Journal of Solid-State Circuits, Volume SC-14, No. 5, pages 867-872 (October 1979).
Another approach is to apply normal gate voltage to the gating transistor during a writing operation, but to apply reduced supply voltage to the four latch transistors of the cell. An example of this technique is disclosed in Smith et al U.S. Pat. No. 3,813,653.
A significant disadvantage of either of these two approaches, i.e. either overdriving the gating transistor or reducing the cell supply voltage during a writing operation, is that implementation is not possible employing CMOS/bulk technology, i.e., fabricating devices on bulk single-crystal substrates, since no voltage build-up can be accomplished in CMOS/bulk. Rather, silicon-on-insulator (SOI) technology must be employed, such as silicon-on-sapphire (SOS), silicon-on-spinel, silicon-on-nitride, or silicon-on-oxide. The insulative substrate provides isolation between the individual transistor devices comprising the overall integrated circuit, permitting voltage differences which cannot exist in CMOS/bulk. Disadvantage of SOI technology, such as SOS technology, are relatively higher cost, interface leakage, and the great care which must be taken to minimize the number of defects in the silicon film comprising the device active portions.